Dual-ported dynamic random access memory (DRAM) devices are used, for example, for storing picture data to be input to a cathode ray tube. The picture data is randomly accessed to write or update the image in memory and then subsequently accessed serially to generate the image on a cathode ray tube. A memory of this type can store images captured by a video camera or other scanning device or it may be used to store images generated by a graphics system.
The image to be displayed is divided into a number of discrete picture elements or pixels. Each pixel represents a physical position on the output display monitor and can have associated with it a color or specific shade of gray. In image and graphics systems, the pixels of a display are each represented by a value stored in the memory device. This memory representation of a display is typically referred to as a frame buffer. A high resolution display typically has an image of 1280 .times.1024 or 1,310,720 pixels. Each pixel value can be represented by 1 to 24 or more bits thus requiring a large amount of memory to store the image. This requirement for large amount of high speed memory leads to the use of the highest density memory parts available for graphic system devices. Typically, DRAMs provide the highest memory density. Due to the nature of video display scan patterns and update rates, a need for even faster access times and a need to decouple the updating of the frame buffer from the scanning out of the stored values (through video generation circuitry) for display on the video monitor was realized.
Video Random Access Memories (VRAM) are a specialized form of DRAMs. They were designed to solve the problem of simultaneously displaying the contents of a graphics frame buffer to the screen while allowing the graphics or image processor to update the frame buffer with new data. Video RAMs contain two Input/Output ports (one for random access and one for serial access) and one address port. These memories are frequently referred to as dual-port memories. In addition to the standard DRAM random access array of rows and columns, a serial access memory (SAM) register has been added to support serial input and output.
Video RAMs of this type are known in the prior art, for example U.S. Pat. No. 4,541,075 to Dill, et al., describes such a memory device. The graphics or image processor updates the frame buffer by writing into the random access array. The serial access memory register is designed to sequentially shift the contents of its buffer to the display independently of the random access array. The only time the random array and the SAM do not operate independently is when the SAM needs to be loaded with new data from the random array. The SAM is loaded by executing a special memory cycle called a read data transfer which copies an entire row or a portion of a row of the data to be sequentially clocked out of the SAM into circuitry which updates the screen.
Second generation VRAMs were enhanced with the ability to transfer data from the DRAM array into half of the SAM, while the other half of the SAM is being scanned out to the display. This is known as a split read transfer. An output status pin known as QSF is sometimes provided to indicate the half of the SAM being scanned out.
In some systems there are two frame buffers, with one being scanned out to the screen while the other is being updated by the graphics or image processor. This is frequently referred to as a double buffered system. The use of two buffers avoids the problem of scanning a partially updated image to the screen resulting in undesirable partial images. In double buffered systems, the two frame buffers are referred to as frame buffer A, FBA, and frame buffer B, FBB.
One application of graphics displays is to segment the screen into a plurality of windows which are independent portions of the screen. Since each window is independent of the others, the current update buffer and the display buffer may differ for different windows. Thus, at any moment in time, one window can be using frame buffer A for update and frame buffer B for display while another window can be using the reverse. This leads to the requirement that the scan out buffer be selectable on a per pixel basis.
A graphics system that does not employ windowing, may have a single full screen display 100 as shown in FIG. IA. The contents of one frame buffer, for example frame buffer B, is displayed while the contents of a second one, frame buffer A is updated. At a certain point in time, the designation of the buffers is swapped so that the contents of frame buffer A is displayed while the contents of frame buffer B is updated.
FIG. 1B illustrates the use of a windowed system. Full screen 100 may be made up of windows such as those labeled 102, 104 and 106. Each application will maintain an indication of which frame buffer is being used for update and which is being used for display. Initially window 1 may be associated with updating frame buffer A, window 2 frame buffer B, and window 3 frame buffer A. The initial display is window 1 from frame buffer B, window 2 from frame buffer A, and window 3 from frame buffer B. Upon the swapping of window 3 between frame buffers, updates for window 1 are into frame buffer A, window 2 frame buffer B, and window 3 frame buffer B, while the display is from frame buffer B, frame buffer A, and frame buffer A, respectively.
One method of implementing double buffered systems is to put the two frame buffers in separate VRAMs. With separate VRAMs it is relatively easy to synchronize the two SAM registers and select pixel data from one or the other VRAM on a per pixel basis. This can be done, for example, by using the Serial Output Enable control pin to only enable the data from the desired frame buffer. However, by placing the frame buffers in separate VRAMS, the cost of the frame buffer will be increased or the drawing rate to the frame buffer will be reduced. Additionally, this design can lead to problems with bus contention if the turn on time of the serial drivers of one VRAM is faster than the turn-off time of the serial drivers of the other VRAMS.
Another method of implementing double buffered systems is described in commonly assigned U.S. patent application Ser. No. 07/352,442, filed May 16, 1989, entitled "Video Ram Double Buffer Select Control", now U.S. Pat. No. 5,065,368, the disclosure of which is incorporated herein by reference. In that application, a serial access memory having a low data register and a high data register memory is described. The low data register represents frame buffer A and the high data register represents frame buffer B, and a select pin is used to select data from either the low data register or the high data register. This design, however, eliminates split read transfer because both the low and high data registers are active at the same time. Therefore, a need exists for extending the SAM data selection approach of U.S. Pat. No. 5,065,368 such that the capability of split read transfer is maintained. A need also exists for providing data selection on a per byte per serial clock cycle basis.